A Profit Evaluation System (PES) for logic cores at early design stage

Author

Lu, Shyue-Kung ; Lee, Tsung-Ying ; Wu, Cheng-Wen

Author_Institution

Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1491

Abstract

In this paper, we propose a Profit Evaluation System (PES) for IC designers. This system will help designers to determine the yield and test plan when specified quality level is given. Type of circuit fabric and raw manufacturing data (i.e., wafer size, wafer cost, defect density and distribution) are given for the system. The outputs of the system are the values of yield and fault coverage that will generate maximal profit. Different yield models and cost models are selectable for the users. Experimental results show that the system can find the optimal yield and test plan for generating the maximal profit. In the future, the building blocks for SOC (system-on-a-chip) designs may be a controller core, embedded SRAM memory, and some dedicated logic. Therefore, we will find the yield models and the cost models for these blocks to make our system suitable for SOC systems

Keywords

integrated circuit design; integrated circuit economics; integrated circuit modelling; integrated circuit testing; integrated circuit yield; logic design; IC design; Profit Evaluation System; controller core; cost model; embedded SRAM memory; fault coverage; logic core; system-on-a-chip; test plan; yield model; Circuit faults; Circuit testing; Control systems; Costs; Fabrics; Logic design; Manufacturing; Semiconductor device modeling; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957497

Filename

957497