A Profit Evaluation System (PES) for logic cores at early design stage

In this paper, we propose a Profit Evaluation System (PES) for IC designers. This system will help designers to determine the yield and test plan when specified quality level is given. Type of circuit fabric and raw manufacturing data (i.e., wafer size, wafer cost, defect density and distribution) are given for the system. The outputs of the system are the values of yield and fault coverage that will generate maximal profit. Different yield models and cost models are selectable for the users. Experimental results show that the system can find the optimal yield and test plan for generating the maximal profit. In the future, the building blocks for SOC (system-on-a-chip) designs may be a controller core, embedded SRAM memory, and some dedicated logic. Therefore, we will find the yield models and the cost models for these blocks to make our system suitable for SOC systems