Impact of Parasitic Elements on the Spurious Triggering Pulse in Synchronous Buck Converter

This paper derives a circuit-level analytical model for describing the mechanism of the spurious triggering pulse in the gate-source voltage of the synchronous MOSFET (SyncFET) in the synchronous buck converter. The model takes into account not only the parasitic capacitances and inductances of the control MOSFET (CtrlFET) and the SyncFET, but also the reverse recovery characteristics of the body diode of the SyncFET. An exhaustive investigation into the impact of all these factors on the spurious triggering pulse is conducted. The spurious triggering pulse can be attributed to two factors. The first one is the positive gate voltage caused by the displacement current through the gate-drain capacitance of the SyncFET, due to the increase in the drain-source voltage. The second one is the negative source voltage caused by the voltage drop across the source inductance of the SyncFET, due to the decrease in the drain current. It is discovered that the gate impedance of the SyncFET would exert different influence on the magnitude of the spurious triggering pulse, depending on the contributions of these two factors. Experimental results affirm that variation in the magnitude of the spurious triggering pulse with each parasitic element can be correctly inferred by the proposed model. Design guidelines for enhancing spurious turn-on immunity are advanced.