• DocumentCode
    1656759
  • Title

    SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films

  • Author

    Chan, Mansun ; Fung, Samuel K H ; Hui, Kelvin Y. ; Hu, Chenming ; Ko, Ping Keung

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1995
  • Firstpage
    631
  • Lastpage
    634
  • Abstract
    The effects of scaling MESA isolated (with sidewall reoxidation) SOI MOSFETs with respect to channel length, channel width, silicon film thickness and buried oxide thickness have been studied experimentally. Characteristics of narrow-width devices have a strong dependence on T Si. In devices with small TSi, narrow-width effect dominates over short channel effect. Thin buried oxide reduces self-heating and short channel effect, but results in a lower intrinsic current drive due to the effect of backside coupling. The trade-offs and limitations for scaling individual dimension in MESA isolated SOI MOSFETs are discussed
  • Keywords
    MOSFET; isolation technology; oxidation; semiconductor technology; semiconductor thin films; silicon-on-insulator; MESA isolated devices; SOI MOSFET design; Si; all-dimensional scaling; backside coupling; buried oxide thickness; channel length; channel width; intrinsic current drive; narrow-width devices; sidewall reoxidation; thin buried oxide; ultra-thin films; Boron; Guidelines; Implants; Isolation technology; Kelvin; MOSFET circuits; Optical films; Oxidation; Semiconductor films; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1995. IEDM '95., International
  • Conference_Location
    Washington, DC
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-2700-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1995.499299
  • Filename
    499299