Design of low-power on-line reconfigurable datapaths using self-checking circuits

Author

Kakarountas, A.P. ; Kokkinos, V. ; Goutis, C.E.

Author_Institution

Dept. of Electr. & Comput. Eng., Patras Univ., Greece

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1565

Abstract

In this paper, a novel technique is illustrated to implement fault-tolerant circuits. On-line testing is used to detect errors and a reconfiguration technique is applied to by-pass the erroneous unit. The main characteristics of this technique are the reduced power dissipation compared to formal implementations and the minimum required time to perform the reconfiguration process. Application of this technique on FIRs is illustrated and a maximum of 40% is saved from the area required for integration, while 33% power reduction is achieved

Keywords

FIR filters; error detection; fault tolerance; integrated circuit design; integrated circuit reliability; reconfigurable architectures; FIRs; IC complexity; erroneous unit by-pass; error detection; fault-tolerant circuits; integrated circuits; integration area; low-power on-line reconfigurable datapath design; on-line testing; power dissipation; power reduction; reconfiguration process time; reconfiguration technique; self-checking circuits; Application specific integrated circuits; Circuit faults; Circuit testing; Control systems; Error correction; Fault tolerance; Fault tolerant systems; Finite impulse response filter; Maintenance; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957515

Filename

957515