Template generation and selection algorithms

Author

Guo, Yuanqing ; Smit, Gerard J M ; Broersma, Hajo ; Heysters, Paul M.

Author_Institution

Twente Univ., Enschede, Netherlands

fYear

2003

Firstpage

2

Lastpage

5

Abstract

The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extract functional equivalent structures, i.e. templates, from a control data flow graph. By inspecting the graph the algorithm generates all the possible templates and the corresponding matches. Using unique serial numbers and circle numbers the algorithm can find all distinct templates with multiple outputs. The template selection algorithm shows how this information can be used in compilers for reconfigurable systems. The objective of the template selection algorithm is to find an efficient cover for an application graph with a minimal number of distinct templates and minimal number of matches.

Keywords

field programmable gate arrays; high level synthesis; logic CAD; microprocessor chips; reconfigurable architectures; system-on-chip; CDFG; FPGA; MONTIUM processor; SoC architecture; application graph; control data flow graph; field programmable gate arrays; functional equivalent structure; high-level design entry tooling; logic circuit design; reconfigurable system; template generation method; template selection algorithm; Clustering algorithms; Data mining; Electronic mail; Field programmable gate arrays; Flow graphs; Multimedia systems; Programmable logic arrays; System-on-a-chip; Tiles; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Print_ISBN

0-7695-1944-X

Type

conf

DOI

10.1109/IWSOC.2003.1212995

Filename

1212995