Optimized datapath design by evolutionary computation

Author

Araùjo, S.G. ; Mesquita, A.C. ; Pedroza, A.C.P.

Author_Institution

Dept. of Electr. Eng., Univ. Fed. do Rio de Janeiro, Brazil

fYear

2003

Firstpage

6

Lastpage

9

Abstract

High-level design entry tools offer a nice framework to deal with today´s complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.

Keywords

circuit layout CAD; genetic algorithms; hardware description languages; high level synthesis; integrated circuit design; system-on-chip; HLS tool; VHDL; area usage; automatic learning paradigm; complex system; datapath design optimization; datapath synthesis; design cycle; digital IC design; evolutionary computation; genetic programming; high level synthesis; high-level design entry tool; multi-objective optimization algorithm; multiobjective function; system-on-chip; timing performance; two-stage optimization algorithm; verilog hardware description languages; Circuits; Design methodology; Design optimization; Evolutionary computation; Genetic algorithms; Genetic programming; Hardware design languages; High level synthesis; Space exploration; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Print_ISBN

0-7695-1944-X

Type

conf

DOI

10.1109/IWSOC.2003.1212996

Filename

1212996