Title :
0.228 μm2 trench cell technologies with bottle-shaped capacitor for 1 Gbit DRAMs
Author :
Ozaki, T. ; Noauchi, M. ; Habu, M. ; Aoki, Hidetaka ; Ishibashi, P. ; Shino, T. ; Hamamoto, T. ; Takashima, D. ; Niiyama, H. ; Nakasugi, T. ; Shibata, T. ; Kato, Y. ; Nishimura, E. ; Hattori, K. ; Magoshi, T. ; Sato, S. ; Yamaguchi, H. ; Sugihara, K.
Author_Institution :
ULSI Res. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
In order to realize 1 Gbit DRAMs, we have developed a 0.228 μm 2 trench type cell. Two methods are employed to shrink the memory cell size. One is a “bottle shaped” capacitor, which has a larger diameter than the opening for the storage node. For this capacitor structure, we have verified 30% capacitance increase keeping the trench opening, sufficiently high breakdown field of capacitor dielectric, and less than 1/1000 of a soft-error rate compared with the conventional one. The other is a 6F2 cell layout suitable for an open-folded-bit-line architecture, which reduces to 75% for the conventional 8F2 cell layout with the same feature size, F. We have also confirmed that a P+ poly gate transistor has a sufficient overlap tolerance (more than 0.1 μm) between the transfer gate and the trench edge by using three-dimensional device simulator. These results strongly support feasibility of our novel cell
Keywords :
DRAM chips; MOS memory circuits; ULSI; capacitors; cellular arrays; integrated circuit technology; isolation technology; 1 Gbit; DRAMs; bottle-shaped capacitor; capacitor dielectric; feature size; memory cell size; open-folded-bit-line architecture; overlap tolerance; poly gate transistor; soft-error rate; three-dimensional device simulator; trench cell technologies; Boron; Capacitance; Capacitors; Controllability; Degradation; Doping; Electrodes; Oxidation; Random access memory; Silicon;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499306
