• DocumentCode
    1657021
  • Title

    A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs

  • Author

    Hada, H. ; Tatsumi, T. ; Miyanaga, K. ; Iwao, S. ; Mori, H. ; Koyama, K.

  • Author_Institution
    ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
  • fYear
    1995
  • Firstpage
    665
  • Lastpage
    668
  • Abstract
    A self-aligned contact pad formation technology for giga-bit DRAMs has been developed using anisotropical selective epitaxial silicon grown at 700°C. Interfacial contact resistance was reduced to approximately one-fifth of that of a conventional poly-Si plugged contact. The smallest memory cell size of 0.24 μm2 with a 0.20 μm design rule can be achieved
  • Keywords
    DRAM chips; ULSI; cellular arrays; contact resistance; integrated circuit metallisation; leakage currents; semiconductor epitaxial layers; semiconductor growth; silicon; vapour phase epitaxial growth; 0.20 micron; 700 degC; Si; anisotropical selective epitaxial material; contact pad formation technology; design rule; gigabit DRAMs; interfacial contact resistance; memory cell size; self-aligned contact technology; Anisotropic magnetoresistance; Capacitors; Contact resistance; Epitaxial growth; Laboratories; National electric code; Random access memory; Silicon; Temperature; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1995. IEDM '95., International
  • Conference_Location
    Washington, DC
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-2700-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1995.499307
  • Filename
    499307
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1657021