Noise contribution in a fully integrated 1-V, 2.5-GHz LNA in CMOS-SOI technology

Author

Tinella, C. ; Fournier, J.M. ; Haidar, J.

Author_Institution

ENSERG, Grenoble, France

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1611

Abstract

This paper presents a study on the contribution of the parasitic elements of the input integrated inductors to the noise figure of a fully integrated low noise amplifier (LNA). The LNA topology is a single-ended common source with inductive degeneration. The optimum trade-off between transistor noise and inductor series resistor noise is demonstrated. Good noise figure is obtained while maintaining sufficient gain and linearity. Simulated results concerning a 2.5 GHz LNA in a 0.25 μm partially depleted SOI-CMOS process, are presented to validate our analysis

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; circuit simulation; inductors; integrated circuit modelling; integrated circuit noise; network topology; silicon-on-insulator; 0.25 micron; 1 V; 2.5 GHz; CMOS-SOI technology; LNA; LNA topology; fully integrated LNA; gain; inductive degeneration; inductor series resistor noise; input integrated inductors; linearity; low noise amplifier; noise contribution; noise figure; parasitic elements; partially depleted SOI-CMOS process; single-ended common source; transistor noise; CMOS technology; Conductivity; Impedance; Inductors; Integrated circuit technology; Linearity; Low-noise amplifiers; Noise figure; Parasitic capacitance; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957526

Filename

957526