A new leakage component caused by the interaction of residual stress and the relative position of poly-Si gate at isolation edge

We report a new junction leakage generation phenomenon which was found at specific junction edges on top of which poly-Si gates ran nearby in a 0.35 μm design rule actual DRAM chip. As more advanced isolation schemes that enabled less bird´s beak were applied, the phenomenon was more evident. After characterizing a set of junction leakage patterns where the relative position of poly gate to the junction edge was systematically varied, a problematic combination of process window and design rule was found and screened out of the actual circuit layout. This leakage component has to be considered to improve the refresh characteristics and stand-by current