A 0.25 μm CMOS technology with 45 Å NO-nitrided oxide

Author

Luo, Marie S C ; Tsui, Paul V G ; Chen, Wei-Ming ; Gilbert, Percy V. ; Maiti, Bikas ; Sitaram, A.R. ; Sun, Shih-Wei

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1995

Firstpage

691

Lastpage

694

Abstract

This paper describes the device design and fabrication of a 0.25 μm CMOS process integrated with 45 Å oxynitride gate dielectric for high-performance logic applications. Channel profile engineering is applied to control short-channel effects. With TiN-capped Co salicide, the gate sheet resistance is reduced to less than 5 Ω/sq at 0.18 μm. Ring oscillator gate delay of 26 ps/stage is accomplished at a supply voltage of 1.8 V

Keywords

CMOS integrated circuits; CMOS logic circuits; dielectric thin films; integrated circuit technology; 0.25 micron; 1.8 V; 45 A; CMOS technology; NO-nitrided oxide; SiNO-Si; TiN-CoSi; TiN-capped Co salicide; channel profile engineering; device design; fabrication; gate sheet resistance reduction; high-performance logic applications; oxynitride gate dielectric; short-channel effects control; CMOS logic circuits; CMOS process; CMOS technology; Delay; Dielectric devices; Fabrication; Logic design; Logic devices; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499313

Filename

499313