An efficient VLSI implementation of logarithmic signal processors

A hybrid logarithmic processor based on the logarithmic number system (LNS) is introduced The LNS exponents of the operands are represented internally using the signed-digit (SD) number system. The LNS exponents, represented traditionally as fixed-point or sign-magnitude numbers, are converted to an SD format and then processed. This allows the parallelism offered by the SD number system at the digital level to be exploited for the implementation of the various operations. In order to reduce the size of the memory tables required for LNS operations like addition to subtraction, a technique for parallel conversion of SD to sign-magnitude numbers is developed. The new processor compares favorably to a previously developed logarithmic processor in terms of computational speed. It also results in a more regular and modal VLSI implementation