Combinational verification by simulations, SAT and BDDs

Author

Radecka, Katarzyna ; Zilic, Zeljko ; Khordoc, Karim

Author_Institution

McGill Univ., Montreal, Que., Canada

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1627

Abstract

In this paper, we consider verification of combinational circuits by test vector simulations. The simulation-based verification under the presence of a fault model uses test pattern generation approach. We show that the test vector generation can be enhanced by techniques used in formal verifications: satisfiability (SAT)- and BDD-based solutions can be combined with the vector simulations. Our method can pass useful information between these disparate approaches. Trade-offs between the three schemes are explored

Keywords

automatic test pattern generation; binary decision diagrams; circuit simulation; combinational circuits; failure analysis; fault location; integrated circuit testing; integrated logic circuits; logic simulation; logic testing; BDD-based solutions; BDDs; SAT; SAT-based solutions; combinational circuits; combinational verification; fault model; in formal verifications; satisfiability-based solutions; simulation-based verification; simulations; test pattern generation; test vector generation; test vector simulations; vector simulations; Arithmetic; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Data structures; Filters; Formal verification;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957530

Filename

957530