A nanoelectronic building block for Spiking Neural Networks

The ability to emulate more closely the behavior of the human brain made Spiking Neural Networks (SNNs) gain prominence between researchers. These highly dense circuits feature large capacity of data processing. Searching for reconfigurable devices, computer scientists and engineers used Field Programmable Gate Arrays (FPGAs) as prototypes for SNNs. However, FPGAs cannot support the high levels of connectivity between neurons in a dense SNN. Besides, implementation with FPGA does not provide improvements regarding power dissipation or scale. Therefore, researchers began to use Networks-on-Chip (NoCs) to interconnect SNNs. The use of NoCs is capable to reduce the number of interconnections and presents a big advantage regarding fault tolerance: redundancy. In this context several configurations combining neurons and routers were proposed. These devices constitute the basic block, present in every node of the NoC. This paper proposes a basic block for a 2D mesh NoC, consisting of a nanoelectronic spiking neuron connected to a router implemented with a look-up table (LUT). The XOR benchmark problem was presented to the SNN in order to evaluate the functionality of the block. A more complex router, suitable for bigger networks is also proposed.