A high performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices

A high performance 0.3 μm CMOS technology has been developed for high speed logic LSIs. A new gate formation technology achieved 0.3 μm gate length MOSFETs by i-line based lithography and new ARC process. An optimized PLDD nMOSFET and buried channel pMOSFET achieved high current drivability without spoiling their reliability in 3.3 V operation. Moreover, ion implantation restricted only for channel/isolation region and SiOF low interlayer dielectric process reduced junction capacitance and wiring capacitance, respectively. Furthermore, CMP planarization process and selective CVD-W filling for contacts/vias achieved borderless design with the improvement of device density. The 0.3 μm CMOS technology has performed 1.2 times improvement from conventional 0.35 μm CMOS technology in a typical critical path of advanced MPUs