Title :
An assessment of the state-of-the-art 0.5 μm bulk CMOS technology for RF applications
Author :
Voinigescu, S.P. ; Tarasewicz, S.W. ; MacElwee, T. ; Ilowski, J.
Author_Institution :
Bell-Northern Res., Ottawa, Ont., Canada
Abstract :
We demonstrate that, given the appropriate layout geometry, state-of-the-art, salicided n-MOSFETs with 0.5 μM drawn gates exhibit similar gm (160 mS/mm), fT (20 GHz), fMAX (37 GHz), and FMIN (1.9 dB @ 3.4 GHz) as the more costly, metal-reinforced SOI or SOS devices of identical gate length. The record fMAX value for 0.5 μm bulk CMOS is comparable to that of self-aligned, double-polysilicon BJTs
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit layout; integrated circuit metallisation; 0.5 micron; 20 GHz; 37 GHz; RF applications; bulk CMOS technology; fMAX value; gate length; layout geometry; salicided n-MOSFET; CMOS technology; Current measurement; Degradation; Fingers; Frequency measurement; Gain measurement; Joining processes; MOSFET circuits; Radio frequency; Scalability;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499320
