Title :
An integrated building block for fast digital filtering
Author :
Rebmann, Volkmar ; Heinrich, Jan ; Lüder, Ernst
Author_Institution :
Inst. fuer Netzwerk- und Systemtheorie, Stuttgart Univ., West Germany
Abstract :
A 2.4-μm CMOS chip is presented for realizing a programmable building block for second-order recursive digital filters. All the fabrication steps lend themselves to high-volume production. Using a fast algorithm, a highly parallel computing scheme, and new algorithmic circuits, the chip allows for a maximum clock frequency of 18 MHz, thus being able to compute every second-order filter function in 56 ns with internal 16-bit fixed-point precision. By cascading several chips, filters of higher degree can be obtained without loss of speed
Keywords :
CMOS integrated circuits; digital filters; parallel architectures; 16 bits; 18 MHz; 2.4 micron; CMOS chip; cascading; fast digital filtering; fixed-point precision; highly parallel computing scheme; integrated building block; maximum clock frequency; second-order filter function; second-order recursive digital filters; Concurrent computing; Delay; Digital filters; Equations; Fabrication; Filtering; Limit-cycles; Parallel processing; State-space methods; Transfer functions;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100653
