Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

Author

Armstrong, Mark A. ; Antoniadis, Dimitri A. ; Sadek, A. ; Ismail, K. ; Stern, Frank

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

1995

Firstpage

761

Lastpage

764

Abstract

A design is presented and computer-simulated for high-mobility Si/SiGe heterojunction CMOS transistors. Comparing 0.2 μm Si/SiGe FETs to bulk Si FETs, an increase is predicted in current drive of 125% and 23% in the p-FET and n-FET, respectively. For given propagation delay (55 ns), simulated loaded ring oscillators at 1.5 V exhibit 4.6 times reduction in power-delay-product compared to bulk Si CMOS oscillators of the same design rules operating at 2.5 V

Keywords

Ge-Si alloys; MOSFET; carrier mobility; elemental semiconductors; semiconductor device models; semiconductor materials; semiconductor quantum wells; silicon; 0.2 micron; 1.5 to 2.5 V; Si-SiGe; heterojunction CMOSFET; heterojunction complementary MOSFET; high-mobility CMOS transistors; planar design; power-delay-product; strained Si/SiGe quantum wells; submicron device; transport modelling; Charge carrier processes; Doping; FETs; Germanium silicon alloys; Heterojunctions; MOS devices; MOSFETs; Ring oscillators; Silicon germanium; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499329

Filename

499329