Title :
A high-speed recursive digital filter using on-line arithmetic
Author :
Brackert, R.H., Jr. ; Willson, A.N., Jr. ; Ercegovac, M.D.
Author_Institution :
Sch. of Eng. & Appl. Sci., California Univ., Los Angeles, CA, USA
Abstract :
A novel design method using online arithmetic (most significant digit first) to implement a high-speed general-purpose integrated circuit for fixed-point recursive digital filtering is described. This approach promises to provide a higher maximum sampling rate than more conventional parallel or serial least-significant-digit-first designs. The method also eliminates entirely the potentially devastating nonlinear oscillations in the filter without affecting the sampling rate. Another characteristic of the approach is that the filter´s sampling rate is independent of the data or coefficient wordlengths and depends only on the available VLSI technology. Some expected worst-case VLSI design results for such a digital filtering chip are presented
Keywords :
VLSI; digital arithmetic; digital filters; VLSI technology; coefficient wordlengths; fixed-point recursive digital filtering; high-speed recursive digital filter; maximum sampling rate; on-line arithmetic; sampling rate; worst-case VLSI design results; Design engineering; Design methodology; Digital arithmetic; Digital filters; Filtering; Fixed-point arithmetic; High speed integrated circuits; IIR filters; Sampling methods; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100655