A high-speed recursive digital filter using on-line arithmetic

A novel design method using online arithmetic (most significant digit first) to implement a high-speed general-purpose integrated circuit for fixed-point recursive digital filtering is described. This approach promises to provide a higher maximum sampling rate than more conventional parallel or serial least-significant-digit-first designs. The method also eliminates entirely the potentially devastating nonlinear oscillations in the filter without affecting the sampling rate. Another characteristic of the approach is that the filter´s sampling rate is independent of the data or coefficient wordlengths and depends only on the available VLSI technology. Some expected worst-case VLSI design results for such a digital filtering chip are presented