A low-power 5 Mb/s turbo decoder for third-generation wireless terminals

In this work, a rate-1/3 8-state log-MAP turbo decoder architecture for third-generation (3G) wireless high-speed data terminals is designed. The simplified log-MAP algorithm is used for the component soft-in soft-out (SISO) decoder. Several architectural and logic level techniques are applied through the design process to reduce area, power consumption, and increase throughput of the turbo decoder. The design is done in stages, each one applying different design techniques. The turbo decoder is written in VHDL, mapped and optimized into 0.18 μm CMOS technology. The synthesized decoder has a core area of about 0.6 mm². It works at a maximum clock frequency of 100 MHz achieving data rates of up to 5 Mbit/s with 5 decoding iterations. The decoder consumes about 63 mW of power, hence, it has an energy efficiency of about 2.5 nJ/b/iteration.