Memristor state to logic mapping for optimal noise margin in memristor memories

Memristor memories provide non-volatile and high density solutions that can overcome some of the challenges faced by CMOS technology. Memristor memories use the memristor as a resistor and depict a logic 1 by a high resistance state and a logic 0 by a low resistance state. Typically, the memristor´s resistance range is divided in half, and a state falling in the lower half depicts a logic 0 and the higher half depicts a logic 1. We show in this paper that it is better to use an unequal division of the range to define the resistance state corresponding to a given logic state. We show how this division can be optimized to provide the highest noise margin.