The ST18940/41: an advanced single-chip digital signal processor

A description is given of the architecture, the internal resources and the performance of a second-generation, monolithic, programmable digital signal processor. The architecture and instruction set of the ST DSP family are designed to allow a straightforward expansion by adding new functions or improving the existing ones in parallel with advances in VLSI technology while ensuring upward software compatibility. The open architecture used for the previous generation (TS68930 designed in NMOS 2-μm technology) lends itself naturally to a structured and hierarchical design approach built around a versatile macrocell library. The architecture is designed to accommodate various DSP family members with different memory sizes and on-chip peripherals, or even with alternative data flow and program control. The chip (designed ST18940) has been designed in 1.2-μm twin-well, double-level-metal CMOS technology. It contains about 230000 transistor sites on a 71-mm² silicon area. With an on-chip crystal oscillator running at 20 MHz, the machine cycle time is 100 ns