A survey on system-on-a-chip design languages

Author

Habibi, Ali ; Tahar, Sofiène

Author_Institution

Electr. & Comput. Eng. Dept., Concordia Univ., Montreal, Que., Canada

fYear

2003

Firstpage

212

Lastpage

215

Abstract

Advancement in the microelectronics era made it possible the integration of a complete yet complex system on a single chip. Over 10 million gates, integrated together and running a real-time optimized software red crossed classical design techniques. Register level will serve as an assembly language for the new design languages or so called system level languages. The problematic is to define a language that can allow the design of such a complex systems. In this paper, we explore different paradigms of state-of-the-art of the System-on-a-Chip (SoC) modeling and design. In particular, this paper presents the main proposals in defining a system level language and discusses their advantages and drawbacks.

Keywords

circuit layout CAD; hardware description languages; integrated circuit design; system-on-chip; assembly language; register level; system level language; system-on-a-chip design language; Computational modeling; Conferences; Design automation; Hardware design languages; Information analysis; Java; Predictive models; Real time systems; System-level design; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Print_ISBN

0-7695-1944-X

Type

conf

DOI

10.1109/IWSOC.2003.1213037

Filename

1213037