Title :
Controlling the device field edge to achieve a low power TFSOI technology
Author :
Racanelli, M. ; Huang, W.M. ; Shin, H.C. ; Foerstner, J. ; Hwang, B.-Y. ; Cheng, S. ; Fejes, P.L. ; Park, H. ; Wetteroth, T. ; Hong, S. ; Shin, H. ; Wilson, S.R.
Author_Institution :
Adv. Custom Technol., Motorola Inc., Mesa, AZ, USA
Abstract :
The impact of stress and dopant redistribution along the field edge of SOI devices on offstate leakage, low voltage performance, and yield is discussed. For the first time, stress caused by overoxidation of the field region is shown to cause excessive device leakage and yield loss. A modified PBL isolation scheme is used to minimize this effect. Dopant redistribution is known to cause field edge leakage and is shown to contribute to narrow channel effects. A novel integration scheme is described to reduce the impact of dopant redistribution and result in a TFSOI technology suitable for low power applications
Keywords :
CMOS integrated circuits; impurity distribution; integrated circuit technology; integrated circuit yield; isolation technology; leakage currents; oxidation; silicon-on-insulator; thin film transistors; Si; device field edge control; dopant redistribution; field edge leakage; low power TFSOI technology; low power applications; low voltage performance; modified PBL isolation scheme; narrow channel effects; offstate leakage; overoxidation stress; thin film SOI; yield; CMOS process; Circuits; Implants; Isolation technology; Leakage current; Low voltage; Parasitic capacitance; Silicon; Stress; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499358
