Asynchronous multipliers with variable-delay counters

Author

Cometta, G. ; Cortadella, Jordi

Author_Institution

Comput. Archit. Dept, Univ. Politecnica de Catalunya, Barcelona, Spain

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

701

Abstract

Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive and fast computations. This paper presents a novel design approach based on the well-known Baugh and Wooley algorithm, particularly appealing for asynchronous implementations and that may be easily mapped into a VLSI circuit. This technique has been applied to the design of a high-speed variable-delay multiplier that resulted to be faster than other synchronous and asynchronous implementations

Keywords

asynchronous circuits; counting circuits; digital arithmetic; integrated circuit design; logic arrays; logic design; multiplying circuits; Baugh Wooley algorithm; VLSI circuit; arithmetic operation; asynchronous multipliers; digital systems; elementary CPL gates; high-speed variable-delay multiplier; variable-delay counters; Algorithm design and analysis; CMOS logic circuits; Computer architecture; Counting circuits; Delay; Digital arithmetic; Digital systems; Encoding; Error correction; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957572

Filename

957572