Title :
W-polycide dual-gate structure for sub-1/4 micron low-voltage CMOS technology
Author :
Bevk, J. ; Georgiou, G.E. ; Frei, M. ; Silverman, P.J. ; Lloyd, E.J. ; Kim, Y. ; Luftman, H. ; Furtsch, M. ; Schiml, T. ; Hillenius, S.J.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
We describe a simple, low cost process, suitable for fabrication of low-voltage sub-1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200 nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30 mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P- and NMOS devices have excellent Ion/Ioff characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10 Ω/□
Keywords :
CMOS integrated circuits; integrated circuit metallisation; ion implantation; rapid thermal annealing; tungsten compounds; 0.25 micron; NMOS devices; PMOS devices; RTA; W-polycide dual-gate structure; WSi-SiO2-Si; fabrication; lateral dopant diffusion; low cost process; low gate stack profile; low-voltage CMOS technology; selective N gate co-implant; sub-1/4 micron LV technology; thermal treatment; threshold voltage shifts; CMOS process; Costs; Fabrication; Leakage current; MOS devices; Nitrogen; Silicides; Threshold voltage; Tungsten; Voltage control;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499360
