Title :
Delay estimation of SCL gates with output buffer
Author :
Alioto, M. ; Palumbo, G. ; Pennisi, S.
Author_Institution :
DEES, Catania Univ., Italy
fDate :
6/23/1905 12:00:00 AM
Abstract :
A strategy to analytically model propagation delay in CMOS SCL gates with output buffer is proposed. The model is obtained by a suitable linearization of the circuit and assuming a dominant-pole behavior. The delay expressions obtained are related to design and process parameters in a simple way. Since they also have an evident physical meaning, the model allows deep understanding of the SCL circuit behavior, and hence they are helpful in the earliest design phases. The accuracy of the model has been checked by simulating an SCL inverter under various bias and load conditions. The error obtained in realistic cases is lower than 20%
Keywords :
CMOS logic circuits; buffer circuits; circuit simulation; delays; integrated circuit modelling; linearisation techniques; logic gates; logic simulation; CMOS; SCL gates; bias conditions; delay expressions; dominant-pole behavior; inverter; linearization; load conditions; output buffer; process parameters; propagation delay; source-coupled logic; CMOS logic circuits; CMOS technology; Delay estimation; Electronic mail; Integrated circuit noise; Inverters; MOSFETs; Parasitic capacitance; Semiconductor device modeling; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957576
