A 0.35 μm ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

Author

Kikuchi, T. ; Onishi, Y. ; Hashimoto, T. ; Yoshida, E. ; Yamaguchi, H. ; Wada, S. ; Tamba, N. ; Watanabe, K. ; Tamaki, Y. ; Ikeda, T.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1995

Firstpage

923

Lastpage

926

Abstract

A 0.35 μm ECL-CMOS technology has been developed to achieve high speed and high density LSIs for mainframe computers. A high speed bipolar transistor with cutoff frequency f_T of 30 GHz and a 30 μm² 6T-CMOS memory cell with a trench isolation are introduced onto an SOI substrate. This technology has been applied to a 40 ps, 120 K gate logic LSI and a 1 ns, 2.3 Mbit SRAM with 50 K gate array

Keywords

BiCMOS logic circuits; BiCMOS memory circuits; SRAM chips; emitter-coupled logic; integrated circuit technology; isolation technology; large scale integration; logic arrays; silicon-on-insulator; 0.35 micron; 1 ns; 2.3 Mbit; 30 GHz; 40 ps; CMOS memory cell; ECL-CMOS process technology; SOI substrate; Si; gate array; high density LSI; high speed bipolar transistor; logic LSI; mega-bits SRAMs; static RAM; trench isolation; Bipolar transistors; CMOS logic circuits; CMOS technology; Electrodes; Epitaxial layers; Isolation technology; Logic arrays; Oxidation; Random access memory; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499367

Filename

499367