DocumentCode
1658609
Title
New test pattern generation units for NPSF oriented memory built-in self test
Author
Chrisarithopoulos, A. ; Haniotakis, Th ; Tsiatouhas, Y. ; Arapoyanni, A.
Author_Institution
Adv. Silicon Solutions Div., Integrated Syst. Dev. S.A, Athens, Greece
Volume
2
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
749
Abstract
In this paper we present the design of deterministic test pattern generation (TPG) units which can be exploited in a built-in self-test (BIST) scheme for memory neighborhood pattern sensitive fault (NPSF) testing. The proposed TPG units generate the required Eulerian sequence of test patterns for memory type-1 NPSF testing
Keywords
automatic test pattern generation; built-in self test; fault location; integrated circuit testing; integrated memory circuits; logic testing; BIST; Eulerian sequence; NPSF oriented memory built-in self test; TPG units; built-in self-test; deterministic test pattern generation units; memory neighborhood pattern sensitive fault testing; memory type-I NPSF testing; test pattern generation units; test patterns; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design engineering; Informatics; Life estimation; Silicon; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957583
Filename
957583
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