DocumentCode
1658616
Title
An efficient mechanism for debugging RTL description
Author
Jiann-Chyi Ran ; Chang, Yi-Yuan ; Lin, Chia-Hung
Author_Institution
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
fYear
2003
Firstpage
370
Lastpage
373
Abstract
In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.
Keywords
diagnostic expert systems; error detection; hardware description languages; high level synthesis; integrated circuit design; RTL description; debugging mechanism; diagnose design errors; diagnosis algorithm; Algorithm design and analysis; Circuits; Clocks; Debugging; Displays; Error correction; Hardware design languages; Process design; Registers; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN
0-7695-1944-X
Type
conf
DOI
10.1109/IWSOC.2003.1213064
Filename
1213064
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