DocumentCode :
1658631
Title :
An enhanced tree-structured scan chain for pseudo-exhaustive testing of VLSI circuits
Author :
Rau, Jiann-Chyi ; Kuo, Kuo-Chun
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
fYear :
2003
Firstpage :
374
Lastpage :
377
Abstract :
As the test pattern requirement of a pseudo-exhaustive testing is fewer than the traditional exhaustive testing, many approaches and architectures are proposed to implement the pseudo-exhaustive testing. Although these methods and architectures employ LFSR to generate the exhaustive random test patterns could successfully cut down the test time, the same problem "invalid test patterns" should still be considered. To avoid the "invalid test patterns", it requires new strategy to solve this problem. Since different seeds dominate different simulation results, seed selection is not arbitrary any more. This paper illustrates the importance of the seed selection, and shows the influence causing by employing various seeds. A suggestive threshold stop point for new strategy, which tries to solve "invalid test patterns" problem, is also defined.
Keywords :
VLSI; automatic test pattern generation; conformance testing; integrated circuit testing; tree data structures; VLSI circuits; pseudo-exhaustive testing; random test pattern; seed selection; threshold stop point; tree-structured scan chain; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit testing; Phase detection; Sequential analysis; System testing; Test pattern generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
Type :
conf
DOI :
10.1109/IWSOC.2003.1213065
Filename :
1213065
Link To Document :
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