Title :
Additional check node to improve the performance of LDPC codes in the error floor region
Author :
Deka, Kuntal ; Rajesh, A. ; Bora, P.K.
Author_Institution :
Indian Inst. of Technol. Guwahati, Guwahati, India
Abstract :
This paper presents a new scheme to reduce the detrimental effect of the trapping sets in the regular and irregular low density parity check (LDPC) codes. By adding only one new check node and properly selecting its edges, the performance in the error floor region can be improved. Simulation results show that the proposed scheme decreases the bit error rate (BER) and frame error rate (FER) significantly in the high signal-to-noise ratio (SNR) region at the expense of negligible rate loss.
Keywords :
error statistics; parity check codes; LDPC code; bit error rate; check node; detrimental effect reduction; error floor region; frame error rate; low density parity check code; signal-to-noise ratio; trapping set; Bit error rate; Charge carrier processes; Decoding; Iterative decoding; Reliability; Signal to noise ratio; Low density parity check (LDPC) codes; error floor; trapping sets;
Conference_Titel :
Communications (NCC), 2012 National Conference on
Conference_Location :
Kharagpur
Print_ISBN :
978-1-4673-0815-1
DOI :
10.1109/NCC.2012.6176774
