DocumentCode
1658947
Title
Five new high-performance multiplexer-based 1-bit full adder cells
Author
Al-Sheraidah, Abdulkarim ; Alhalabi, Bassem ; Bui, Hung Tien
Author_Institution
Dept. of Comput. Sci. & Eng., Florida Atlantic Univ., Boca Raton, FL, USA
Volume
2
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
807
Abstract
Five new multiplexer-based architectures for 1-bit full adder cell design are presented. Implementing with the pass-gate CMOS multiplexer, results in five distinct adders. Those adder cells along with the conventional 28-transistor CMOS adder are tested using H-Spice under 6 different frequencies and 6 different loads. Testing results shows the new cells exhibit on average 21.7% increase in sum signal speed, and 19.9% increase in carry out signal speed over the conventional 28-transistor CMOS adder, with power-delay product savings reaching up to 18.4%
Keywords
CMOS logic circuits; SPICE; adders; cellular arrays; logic simulation; multiplexing equipment; H-Spice; carry out signal speed; full adder cell design; multiplexer-based architectures; pass-gate CMOS multiplexer; power-delay product savings; Adders; Circuit testing; Computer architecture; Computer science; Delay; Design engineering; Explosives; Frequency; Multiplexing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957597
Filename
957597
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