On placement and routing of wafer scale memory

Author

Sung, Li-An ; Jiang, Iris Hui-Ru ; Chang, Yoh-Wen ; Jou, Jing-Yang ; Wu, Jiin-Chuan ; Feng, Tai-Sheng

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

883

Abstract

The progress of computer technology triggers the requirement of high speed and large volume memory. In modern manufacturing, a memory module is integrated by packaged memory chips on a printed circuit board. This paper proposes two architectures directly to integrate a memory module at the wafer level before packaging. This method can reduce the area, enhance the performance, and save the packaging cost. A polynomial time algorithm is presented to find the placement that minimizes the critical delay of the module. The routing is subsequently applied, and laser cutting technology is adopted to remove the unnecessary connections. Experimental results show that our approaches are very efficient and effective. A 64 M×128 bit module is completed in 348.38 second runtime and 4664 KB memory, and the delay is improved 88.67%

Keywords

circuit layout CAD; integrated circuit layout; integrated memory circuits; network routing; random-access storage; wafer-scale integration; 4664 KB; SDRAM; critical delay minimisation; dynamic random access memory; laser cutting technology; memory module; placement; polynomial time algorithm; routing; synchronous DRAM; wafer scale memory; Computer architecture; Costs; Delay; Integrated circuit manufacture; Integrated circuit technology; Packaging; Polynomials; Printed circuits; Routing; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957615

Filename

957615