DocumentCode
1659561
Title
A novel dynamically programmable arithmetic array using code division multiple access bus
Author
Tan, Boon-Keat ; Yoshimura, Ryuji ; Matsuoka, Toshimasa ; Taniguchi, Kenji
Author_Institution
Dept. of E.I.S., Osaka Univ., Japan
Volume
2
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
913
Abstract
A new architecture-based reconfigurable device, Dynamically Programmable Arithmetic Array (DPAA), which is proposed to overcome design issues such as low chip area utilization, low routing flexibility and long reconfiguration time in most reconfigurable architectures. The DPAA consists of various basic arithmetic blocks which are interconnected through a differential multiple access bus. Connections between the arithmetic blocks are done virtually through code matching and thus, 100% routing flexibility can be achieved. Fault tolerance can be realized without allocating specialized spare elements or applying special techniques. The DPAA also features dynamical programmable, higher-density, easier compilation and less time for reconfiguration compared with conventional reconfigurable architectures
Keywords
code division multiple access; digital arithmetic; fault tolerance; network routing; programmable logic arrays; reconfigurable architectures; system buses; chip area; circuit design; code division multiple access bus; code matching; dynamically programmable arithmetic array; fault tolerance; reconfigurable architecture; routing flexibility; Arithmetic; Circuit noise; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Multiaccess communication; Reconfigurable architectures; Routing; Switching circuits; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957621
Filename
957621
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