Title :
A code transformation-based methodology for improving I-cache performance
Author :
Liveris, N. ; Zervas, N.D. ; Kakaroudas, A.P. ; Goutis, C.E.
Author_Institution :
VLSI Design Lab, Patras Univ., Greece
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper focuses on I-cache behaviour enhancement through the application of high-level code transformations. Specifically, a flow for the iterative application of the I-Cache performance optimizing transformations is proposed. The procedure of applying transformation is driven by a set of analytical equations, which receive parameters related to code and I-cache structure and predict the number of I-cache misses
Keywords :
cache storage; codes; iterative methods; I-cache memory; high-level code transformation; iterative application; performance optimization; Bridges; Embedded system; Equations; Performance analysis; Prefetching; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957622
