Title :
nSET: Novel simulation method for single-electron tunnel device with 1-Dimension multiple islands
Author :
Sui, Bingcai ; Chi, Yaqing ; Fang, Liang
Author_Institution :
Nat. Lab. for Parallel & Distrib. Process., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
Single-electronic transistors (SETs) are considered as the attractive candidates for post-CMOS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. A new simulation method-nSET, is introduced in this paper. Compared with other methods, nSET can simulate the SET device with 1-dimension multiple islands with high speed and accuracy. Through the comparison, it can be get that nSET is accurate and fast compared with the classical Monte Carlo (MC) simulator, and is very useful for the ASIC design of SET devices.
Keywords :
CMOS integrated circuits; Monte Carlo methods; VLSI; application specific integrated circuits; single electron transistors; 1D multiislands; 1D multiple islands; ASIC design; Monte Carlo simulator; low power consumption; nSET; post-CMOS VLSI; single electronic transistors; single-electron tunnel device; ultra-small size; Application specific integrated circuits; Capacitance; Circuit simulation; Discrete event simulation; Electrostatics; Energy consumption; Programming profession; Single electron transistors; Tunneling; Very large scale integration; Monte Carlo simulation; multiple islands; single-electron transistor; single-electron tunneling device;
Conference_Titel :
Nanoelectronics Conference (INEC), 2010 3rd International
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-3543-2
Electronic_ISBN :
978-1-4244-3544-9
DOI :
10.1109/INEC.2010.5424625
