Leveraging block decisions and aggregation in the ShareStreams QoS architecture

ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design choices and tradeoffs made in the development of a endsystem/host-based router realization of the ShareStreams architecture. We evaluate the impact of block decisions and aggregation on the ShareStreams architecture. Using processor resources for queuing and data movement, and FPGA hardware for accelerating stream selection and stream priority updates, ShareStreams can easily meet the wire-speeds of 10 Gbit/s links. This allows provision of customized scheduling solutions and interoperability of scheduling disciplines. Our hardware implemented in the Xilinx Virtex I family easily scales from 4 to 32 stream-slots on a single chip. A host-based router prototype with FPGA PCI card under systems software control, can provide scheduling support for a mix of EDF, static-priority and fair-share streams based on user specifications and meet the temporal bounds and packet-time requirements of multi-gigabit links.