• DocumentCode
    1660162
  • Title

    Non-robust delay test pattern generation based on stuck-at TPG

  • Author

    Meyer, Volker H W ; Anheier, Walter ; Sticht, Arne

  • Author_Institution
    ikom - Center for Inf. & Commun. Technol., Bremen Univ., Germany
  • Volume
    2
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    1007
  • Abstract
    An approach to generate test pattern for the path delay fault model using a modified stuck-at TPG tool which has been used for industrial purposes for years is presented. We discuss constraints derived by the definition of non-robust delay tests and show that, under some circumstances, the requirements accepted in literature are not sufficient to derive non-robust tests due to possible test invalidation, even in the absence of any additional faulty delay. Finally, we discuss possible constraints which have influence on the test quality and show that test generation for robust tests can not be tackled if a stuck-at TPG tool is used without any delay fault simulation
  • Keywords
    automatic test pattern generation; delays; digital integrated circuits; fault diagnosis; integrated circuit testing; ATPG; delay test pattern generation; modified stuck-at TPG tool; nonrobust delay tests; nonrobust test pattern generation; path delay fault model; Added delay; Circuit faults; Circuit testing; Clocks; Communication industry; Communications technology; Delay effects; Robustness; Semiconductor device testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
  • Print_ISBN
    0-7803-7057-0
  • Type

    conf

  • DOI
    10.1109/ICECS.2001.957645
  • Filename
    957645