On the yield of compiler-based eSRAMs

Author

Wang, X. ; Ottavi, M. ; Meyer, F. ; Lombardi, F.

Author_Institution

IBM Corp., Essex Junction, VT, USA

fYear

2004

Firstpage

11

Lastpage

19

Abstract

This work presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as a design case.

Keywords

SRAM chips; application specific integrated circuits; circuit layout CAD; integrated circuit design; integrated circuit yield; logic CAD; redundancy; array size; compiler-based array yield analysis; compiler-based eSRAM; embedded SRAM; kernel design constructs; line organization; manufacturing yield; memory architecture; memory compiler; multiple SRAM ASIC chip; redundancy; Application specific integrated circuits; Circuit faults; Decoding; Integrated circuit yield; Kernel; Manufacturing industries; Memory architecture; Pulp manufacturing; Random access memory; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2241-6

Type

conf

DOI

10.1109/DFTVS.2004.1347820

Filename

1347820