A configurable parallel neurocomputer

Author

Strey, Alfred ; Avellana, Narcis ; Holgado, Raul ; Capillas, Ramon ; Alberto Fernandez, J. ; Valderrama, Elena

Author_Institution

Ulm Univ., Germany

fYear

1995

Firstpage

55

Lastpage

58

Abstract

The paper presents the architecture of a new configurable parallel neurocomputer optimized for the high-speed simulation of neural networks. Its main system feature is the reconfigurability of a new arithmetical unit chip which supports several accuracies in all typical neural network operations. If the required accuracy is decreased the degree of parallelism inside the chip can be increased by a dynamical reconfiguration of the hardware resources. The system also offers a good scalability: for the simulation of large neural networks the system performance can easily be increased by using several arithmetical unit chips operating in parallel

Keywords

neural chips; neural net architecture; parallel architectures; parallel machines; reconfigurable architectures; virtual machines; arithmetical unit chip; configurable parallel neurocomputer architecture; dynamical hardware resource reconfiguration; high-speed neural network simulation; neural network operations; parallelism; reconfigurability; system performance; Computational Intelligence Society; Computational modeling; Computer simulation; Encoding; Hardware; Neural networks; Neurons; Parallel processing; Scalability; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Artificial Neural Networks and Expert Systems, 1995. Proceedings., Second New Zealand International Two-Stream Conference on

Conference_Location

Dunedin

Print_ISBN

0-8186-7174-2

Type

conf

DOI

10.1109/ANNES.1995.499438

Filename

499438