DocumentCode
1660355
Title
Co-design and refinement for safety critical systems
Author
Ajer, A. ; Devienne, Philippe
Author_Institution
Univ. of Sci. & Technol. of Lille 1, France
fYear
2004
Firstpage
78
Lastpage
86
Abstract
In this paper we focus on design entry of complex systems, that is, the highest abstract tier of the global system without implementation choices to such and such technologies. At this very first level, the use of a formal specification language is more and more considered as the foundation of a real validation process. What we would like to emphasize is that from a formal design entry, project management can be formally controlled by formal refinement. We propose an architecture that is based upon stepwise refinement of a formal model to achieve controllable implementations. This leads to implementations that are highly effective, but remain formally related to the first formal specification. Partitioning, fault tolerance, and system management are seen as particular cases of refinement in order to conceptualize systems correct by proven construction. In this paper, we present the basic principles of system methodologies and describe the methodology based on the refinement paradigm. In order to prove this approach, we have developed the B-HDL Tool based on VHDL (digital circuits) and B method (formal language based on set theory and logic). The benefits of such tools would be an amazing productivity gain, a better reuse of automation and a formal redundancy management.
Keywords
fault tolerance; formal specification; hardware description languages; hardware-software codesign; logic partitioning; project management; redundancy; safety; set theory; B method; B-HDL tool; VHDL; automation reuse; co-design; fault tolerance; formal mode stepwise refinement; formal redundancy management; formal specification language; logic; partitioning; productivity gain; project management; safety critical systems; set theory; system management; validation process; Automation; Digital circuits; Fault tolerant systems; Formal languages; Formal specifications; Logic circuits; Productivity; Project management; Safety; Set theory;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2241-6
Type
conf
DOI
10.1109/DFTVS.2004.1347827
Filename
1347827
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