Title :
Noise effects on performance of low power design schemes in deep submicron regime [CMOS digital ICs]
Author :
Abbas, Mohamed ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electron. Eng., Univ. of Tokyo, Japan
Abstract :
The noise immunity of modern CMOS digital design has become an important metric, as well as its power consumption. In this paper, we evaluate the noise immunity of static CMOS low power design schemes in terms of logic and delay error. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron is presented. Then the model is applied to the most well known low power design schemes to find the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance could be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 μm CMOS technology.
Keywords :
CMOS digital integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; logic design; low-power electronics; 0.18 micron; CMOS digital design; HSPICE; delay error; dual threshold voltage scheme; logic error; low power design; noise immunity; noise source models; static CMOS; CMOS logic circuits; CMOS technology; Circuit noise; Circuit optimization; Delay; Energy consumption; Logic design; Noise robustness; Semiconductor device modeling; Threshold voltage;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347828
