Fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and 35 ps jitter

Author

Xu, Chao ; Sargeant, Winslow ; Laker, Kenneth ; Van der Spiegel, Jan

Author_Institution

Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

55

Abstract

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 μm, 2.5 V digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 μm CMOS technology. Also it has very low peak-to-peak jitter less than ±35 ps at 1.25 GHz output frequency

Keywords

CMOS digital integrated circuits; digital phase locked loops; jitter; optical communication equipment; synchronisation; 0.24 micron; 1.25 GHz; 2.5 V; 30 MHz to 2 GHz; 35 ps; digital CMOS technology; fiber-optic communication chip; locking range; multi-gigabit-per-second clock recovery circuits; output frequency; peak-to-peak jitter; phase-locked loop; CMOS technology; Clocks; Filters; Frequency; Integrated circuit technology; Jitter; Phase locked loops; Tuning; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957665

Filename

957665