A fading algorithm for sequential fault diagnosis [logic IC testing]

Fault diagnosis algorithms for logic designs with only partial scan support remains inadequate so far because of the difficulties in dealing with the sequential fault effect. In this paper, we enhance our previous symbolic techniques to address such a challenge. Along with the baseline enhancement, we also propose a fading scheme that can effectively reduce the potentially huge memory requirement and long running time without sacrificing much accuracy. This fading algorithm incorporates a commonly used concept called ´local fault effect´, using symbolic techniques. Experimental results show that sequential fault diagnosis can actually be done effectively and accurately with reasonable CPU time.