Clock jitter insensitive continuous-time /spl Sigma//spl Delta/ modulators

Timing errors due to clock jitter are one of the most severe problems, when building continuous time (CT) SigmaDelta modulators. This is due to a strong dependence of the modulator resolution on the timing errors of the clock. The methodology presented in this paper allows the implementation of jitter insensitive CT EA modulators. Therefore a modified switched capacitor feedback structure has been derived to reduce the sensitivity to clock jitter, while keeping the advantages of the CT design concerning speed and power. The problem of jitter noise is investigated analytically, and the new approach is described. An easy method to implement CT modulators with the shown jitter insensitivity is presented. Finally the constraints of the approach are shown.