Title :
"Victim gate" crosstalk fault model
Author_Institution :
Ferrara Univ., Italy
Abstract :
Crosstalk faults may produce either glitches or additional delays. The impact of glitches on the behavior of synchronous digital ICs has been shown to be less relevant than that of the additional delays. Glitches may be filtered out by the inertial effects of gates. The driving capabilities of gates performing such a filtering, however, are impaired. Therefore, a transition propagating through one of them may be delayed because of a glitch on another input of the gate. This crosstalk induced effect (here referred to as "victim gate" crosstalk fault) is analyzed from a quantitative point of view. In particular, it is shown that it should be explicitly considered in path delay test generation in the presence of crosstalk faults. Simulations show that test sequences neglecting victim gate crosstalk faults present a relevant escape probability.
Keywords :
integrated circuit modelling; integrated circuit noise; integrated circuit testing; interference (signal); logic testing; timing; crosstalk fault delays; crosstalk induced effects; crosstalk noise; gate driving capabilities; gate inertial effects; glitch filtering; path delay test generation; synchronous digital IC; victim gate crosstalk fault model; Crosstalk; Fault tolerant systems; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347840