An application specific processor for a multi-system navigation receiver

Author

Aardoom, Eric ; Stravers, Paul

Author_Institution

Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

1992

Firstpage

128

Lastpage

131

Abstract

An application-specific processor for use as the central component for both signal processing and general control tasks of a combined GPS/Loran-C/Omega/MIS navigation receiver is described. It is the first implementation of the transport-triggered Move architecture framework. Vector registers are included to enhance signal processing performance, resulting in a single-cycle multiply-accumulate operation, without compromising scalar performance. The projected clock frequency of this implementation is 125 MHz for a 180000-transistor, 1.6-μm C MOS sea-of-gates chip

Keywords

CMOS integrated circuits; digital signal processing chips; radionavigation; signal processing; 1.6 micron; 125 MHz; C MOS sea-of-gates chip; application-specific processor; clock frequency; combined GPS/Loran-C/Omega/MIS navigation receiver; global positioning system; multisystem navigation receiver; scalar performance; signal processing; transport-triggered Move architecture framework; vector registers; Application specific processors; Computer architecture; Digital filters; Filtering; Finite impulse response filter; Frequency; IIR filters; Navigation; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276192

Filename

276192