Generic and programmable Timing Generator for CCD detectors

Charge Coupled Devices (CCD) detectors are frequently used in imaging payloads developed for different satellite applications like space based astronomy and earth observations. CCD´s are being used for onboard/satellite applications as it provides lower noise and higher dynamic range than CMOS detectors. CCDs are available in various architectures hence design of Timing Generator is planned based on CCD requirements. This paper discusses design methodology for generic timing generator which is completely programmable and supports various CCD architectures. The aim of design is to provide flexibility in terms of number of different types of clocks, effective image area and readout features with respect to various CCD architectures. Different supported CCD architectures, overall clock requirements, required readout features are studied and design architecture is worked out. The RTL design of Timing Generator is done using VHDL and block level verification is done using Verilog. The design is targeted to Xilinx Virtex-6 LX FPGA.