Title :
IC design automation from circuit level optimization to retargetable layout
Author :
Jingnan, Xu ; Serras, J. ; Oliveira, M. ; Belo, R. ; Bugalho, M. ; Vital, J. ; Horta, N. ; Franca, J.
Author_Institution :
IST Center for Microsystems, Instituto Superior Tecnico, Lisbon, Portugal
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper describes a new analog and mixed-signal IC design automation environment including both multilevel optimization and layout generation based on retargeting methodologies. The circuit/system level optimization is achieved by applying a simulated annealing technique together with heuristic based rules, for constraint generation, to parametrized circuit descriptions. The layout generation is attained by automatically applying the sized schematic to reusable physical layouts of analog and mixed-signal blocks, built based on high-functionality pCells which are fully independent from technologies. The design automation methodology is illustrated with practical examples
Keywords :
analogue integrated circuits; circuit CAD; circuit layout CAD; circuit optimisation; integrated circuit design; integrated circuit layout; mixed analogue-digital integrated circuits; simulated annealing; IC design automation; analog IC design environment; circuit level optimization; constraint generation; design automation methodology; heuristic based rules; high-functionality pCells; layout generation; mixed-signal IC design environment; multilevel optimization; parametrized circuit descriptions; retargetable layout; retargeting methodologies; reusable physical layouts; simulated annealing technique; sized schematic; Analog integrated circuits; Circuit simulation; Constraint optimization; Cost function; Design automation; Design optimization; Integrated circuit layout; Integrated circuit modeling; Kernel; Simulated annealing;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957682